This invention relates to interconnection system for semiconductor integrated Circuits--in particular to multilayer interconnections.
In the development of interconnection system for very large scale integration (VLSI) circuits, the devices have been shrunk to sub-micron dimensions. The speed of sub-micron transistors is very high, such that the speed of an integrated circuit (IC) is now limited by the interconnection rather than the transistor itself
What limits the speed of the interconnection is the finite resistivity of the interconnection material. Traditionally, aluminum has been used in the past. However the resistivity of aluminum is higher than copper. Therefore, the trend today for high speed IC development is to use copper as interconnections. Another trend today for high packing density is to use multiple layer interconnections for complicated ICs.
One promising approach is the "dual damascene" interconnection technique, where a contact and an interconnection via hole are masked and etched in succession in oxide layers. The contact plug and the interconnection which buries the via hole are formed with one single metal deposition and single chemical-mechanical planarization process. The process is especially suitable for copper interconnection, because the copper cannot be readily etched by plasma, which is widely used for other etching processes in IC fabrication.
There are other process integration problems in fabricating this dual damascene interconnection. The difficulty arises when the second interconnection is masked and patterned after the first via hole for contacting the bottom is masked and patterned. Since the upper contact of the via hole invariably overlaps the interconnecting line, the photoresist for patterning the interconnection fills up the opening for the via hole in the oxide completely. During exposure, the photoresist in the opening experiences different focusing from the photoresist on top of the oxide due to the different amount of photoresist development and due to unevenness of the photoresist, the resultant interconnection pattern is distorted and dimensional control is very difficult. The problem also exists when the mask sequence is reversed.
Furthermore, in circuit design, a margin must be allowed around the contact of the upper via hole plug. Otherwise, the etched interconnection pattern may miss the contact. When a border is made around the contact to allow for misalignment, the density of the IC is compromised.
Another problem of using copper is atom migration due to diffusion.